1. Field of Invention
The present invention relates to a memory device and a fabrication method thereof. More particularly, the present invention relates to a multi-level memory cell and a fabrication method thereof.
2. Description of Related Art
A flash memory device provides the property of multiple entries, retrievals and erasures of data. Moreover, the stored information is retained even electrical power is interrupted. As a result, a non-volatile memory device is widely used in personal computers and electronic devices.
This type of erasable and programmable read-only device employs doped polysilicon to fabricate the floating gate and the control gate. When a memory device performs a programming operation, electrons that are injected into the floating gate are evenly distributed in the entire polysilicon floating gate layer. However, the presence of defects in the tunneling oxide layer underneath the polysilicon silicon floating gate would lead to a current leakage of the device, adversely affecting the reliability of the device.
To resolve the current leakage problem of an electrically erasable programmable read-only memory device, the conventional approach is to replace the polysilicon floating gate with a charge trapping layer. The charge trapping layer is, for example, a silicon nitride layer. This type of silicon nitride charge trapping layer is sandwiched by an upper and a lower silicon oxide layer, which forms a stacked gate structure that includes a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. The EEPROM with this type of stacked gate structure is known as a SONOS read-only memory device. When a voltage is applied to the control gate and the source/drain region of this type of device to perform the programming operation, hot electrons are generated in the channel near the drain region. Since silicon nitride includes the charge trapping characteristics, the charges that are injected into the charge trapping layer are not evenly distributed in the entire charge trapping layer. Instead, these charges are localized in a certain region of the charge trapping layer. Since the charges are localized in a certain region of the charge trapping layer, it is less sensitive to the defects in the tunneling oxide layer. The current leakage problem of the device is thus mitigated.
FIG. 1 is a schematic diagram illustrating the cross-sectional view of a SONOS read-only memory device according to the prior art. Referring to FIG. 1, a SONOS read-only memory cell includes a substrate 100, a composite dielectric layer 102 with a silicon oxide 102a/silicon nitride 102b/silicon oxide 102c structure, a control gate 104, a drain region 106a, a source region 106b and a channel region 108. The silicon oxide 102a/silicon nitride 102b/silicon oxide 102c composite dielectric layer 102 and the control gate 104 are sequentially disposed on the substrate 100 to form a stacked gate structure 110. Further, the channel region is configured in the substrate 100 underneath the stacked gate structure 110, whereas the drain region 106a, the source region 106b are configured in the substrate 100 beside both sides of the stacked gate structure 110.
A higher integration of integrated circuits by further miniaturizing of devices can be achieved by reducing the control gate length of the SONOS memory device. However, as the gate length is being reduced, the underlying channel length is also being reduced. Thus, during the programming of such a memory cell, an abnormal punch through easily occurs between the source region and the drain region, adversely affecting the electrical performance of the memory device.
Further, the application of software by computers has increased tremendously. The capacity of a memory device needs to be increased accordingly. The demands for a small dimension memory device with a large memory capacity thereby increases, which strongly suggests that a modification to the structure and the fabrication method for the conventional SONOS memory device is expected.